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| author | Richard Henderson | 2018-03-09 18:09:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-03-09 18:09:43 +0100 |
| commit | 85fc716732bc6e85a634335847999f411269f282 (patch) | |
| tree | 15ae6a9a0e2d85baa27d03c67af20b749fd9be6c /target/arm/cpu.h | |
| parent | Implement support for i.MX7 Sabre board (diff) | |
| download | qemu-85fc716732bc6e85a634335847999f411269f282.tar.gz qemu-85fc716732bc6e85a634335847999f411269f282.tar.xz qemu-85fc716732bc6e85a634335847999f411269f282.zip | |
linux-user: Implement aarch64 PR_SVE_SET/GET_VL
As an implementation choice, widening VL has zeroed the
previously inaccessible portion of the sve registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180303143823.27055-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3fa8fdad21..36711cdb50 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -866,6 +866,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); #endif target_ulong do_arm_semihosting(CPUARMState *env); |