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| author | Peter Maydell | 2020-02-24 18:28:46 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-28 17:14:57 +0100 |
| commit | a1229109dec4375259d3fff99f362405aab7917a (patch) | |
| tree | fa861ddfe41b9f6e1864945ecfc7206be3af1cb9 /target/arm/cpu.h | |
| parent | target/arm: Implement v8.3-RCPC (diff) | |
| download | qemu-a1229109dec4375259d3fff99f362405aab7917a.tar.gz qemu-a1229109dec4375259d3fff99f362405aab7917a.tar.xz qemu-a1229109dec4375259d3fff99f362405aab7917a.zip | |
target/arm: Implement v8.4-RCPC
The v8.4-RCPC extension implements some new instructions:
* LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW
* STLUR, STLURB, STLURH
These are all in a new subgroup of encodings that sits below the
top-level "Loads and Stores" group in the Arm ARM.
The STLUR* instructions have standard store-release semantics; the
LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose
to implement them as the slightly stronger Load-Acquire.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224172846.13053-4-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff30985ead..ce1e2a090e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3779,6 +3779,11 @@ static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; } +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ |