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| author | Richard Henderson | 2019-03-01 21:04:54 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-03-05 16:55:07 +0100 |
| commit | cb570bd318beb2ecce83cabf8016dacceb824dce (patch) | |
| tree | ad5142b29fa3d0ddc0d3a4e74e2042783513ab01 /target/arm/cpu.h | |
| parent | target/arm: Implement ARMv8.0-SB (diff) | |
| download | qemu-cb570bd318beb2ecce83cabf8016dacceb824dce.tar.gz qemu-cb570bd318beb2ecce83cabf8016dacceb824dce.tar.xz qemu-cb570bd318beb2ecce83cabf8016dacceb824dce.zip | |
target/arm: Implement ARMv8.0-PredInv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 361e51143c..c822f94236 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_SW (1U << 10) /* v7 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3312,6 +3313,11 @@ static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; } +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3455,6 +3461,11 @@ static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; } +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ |