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| author | Richard Henderson | 2022-07-08 17:15:12 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-11 14:19:35 +0200 |
| commit | 0d935760346b7ea07cbf5f63667151198012c922 (patch) | |
| tree | b0997ab4334a9d8da88bc56f9e73f64911f0045c /target/arm/sve.decode | |
| parent | target/arm: Handle SME in sve_access_check (diff) | |
| download | qemu-0d935760346b7ea07cbf5f63667151198012c922.tar.gz qemu-0d935760346b7ea07cbf5f63667151198012c922.tar.xz qemu-0d935760346b7ea07cbf5f63667151198012c922.zip | |
target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 908643d7d9..95af08c139 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 ### SVE Bitwise Shift - Unpredicated Group |