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| author | Peter Maydell | 2020-11-19 22:55:52 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | 4018818840f499d0a478508aedbb6802c8eae928 (patch) | |
| tree | 2f8e62097421b2fdc5fdc8dc9b7f7e5f83ca1bd5 /target/arm | |
| parent | target/arm: Implement v8.1M PXN extension (diff) | |
| download | qemu-4018818840f499d0a478508aedbb6802c8eae928.tar.gz qemu-4018818840f499d0a478508aedbb6802c8eae928.tar.xz qemu-4018818840f499d0a478508aedbb6802c8eae928.zip | |
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
In arm_cpu_realizefn() we check whether the board code disabled EL3
via the has_el3 CPU object property, which we create if the CPU
starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
the ID_PFR1 and ID_AA64PFR0 registers.
This codepath was incorrectly being taken for M-profile CPUs, which
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
the M-profile Security extension and so should have non-zero values
in the ID_PFR1.Security field.
Restrict the handling of the feature flag to A/R-profile cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-4-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a..40f3f798b2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1674,7 +1674,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } - if (!cpu->has_el3) { + if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { /* If the has_el3 CPU property is disabled then we need to disable the * feature. */ |