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| author | Richard Henderson | 2021-01-13 07:26:47 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | b64ee454a4a086ed459bcda4c0bbb54e197841e4 (patch) | |
| tree | 198952acbae1e2ee9b27b6d76ecf8c1a1821d6fd /target/arm | |
| parent | target/arm: refactor vae1_tlbmask() (diff) | |
| download | qemu-b64ee454a4a086ed459bcda4c0bbb54e197841e4.tar.gz qemu-b64ee454a4a086ed459bcda4c0bbb54e197841e4.tar.xz qemu-b64ee454a4a086ed459bcda4c0bbb54e197841e4.zip | |
target/arm: Introduce PREDDESC field definitions
SVE predicate operations cannot use the "usual" simd_desc
encoding, because the lengths are not a multiple of 8.
But we were abusing the SIMD_* fields to store values anyway.
This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.
Introduce a new set of field definitions for exclusive use
of predicates, so that it is obvious what kind of predicate
we are manipulating. To be used in future patches.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/internals.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index 27cc93f15a..853fa88fd6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1349,6 +1349,15 @@ void arm_log_exception(int idx); #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) /* + * SVE predicates are 1/8 the size of SVE vectors, and cannot use + * the same simd_desc() encoding due to restrictions on size. + * Use these instead. + */ +FIELD(PREDDESC, OPRSZ, 0, 6) +FIELD(PREDDESC, ESZ, 6, 2) +FIELD(PREDDESC, DATA, 8, 24) + +/* * The SVE simd_data field, for memory ops, contains either * rd (5 bits) or a shift count (2 bits). */ |