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| author | Cathy Zhang | 2020-12-16 23:40:02 +0100 |
|---|---|---|
| committer | Eduardo Habkost | 2020-12-16 21:50:33 +0100 |
| commit | 40399ecb6959ae696c235097c773d776392fde1f (patch) | |
| tree | d10fa5dea0a21837957c13f43389322e417e82c3 /target/i386/tcg/excp_helper.c | |
| parent | i386: move hyperv_limits initialization to x86_cpu_realizefn() (diff) | |
| download | qemu-40399ecb6959ae696c235097c773d776392fde1f.tar.gz qemu-40399ecb6959ae696c235097c773d776392fde1f.tar.xz qemu-40399ecb6959ae696c235097c773d776392fde1f.zip | |
x86/cpu: Add AVX512_FP16 cpu feature
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].
Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/tcg/excp_helper.c')
0 files changed, 0 insertions, 0 deletions