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| author | Philippe Mathieu-Daudé | 2021-02-14 18:58:37 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-02-21 19:42:34 +0100 |
| commit | 3bc313c4f51a213ebcb172286b575f8d591c634f (patch) | |
| tree | 96ee86484e8f902c55786f2d084770ed2cae1d0f /target/mips | |
| parent | target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers (diff) | |
| download | qemu-3bc313c4f51a213ebcb172286b575f8d591c634f.tar.gz qemu-3bc313c4f51a213ebcb172286b575f8d591c634f.tar.xz qemu-3bc313c4f51a213ebcb172286b575f8d591c634f.zip | |
target/mips: Use GPR move functions in gen_HILO1_tx79()
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-8-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 21 |
1 files changed, 4 insertions, 17 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index a303c36be3..70891c37cd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, /* Copy GPR to and from TX79 HI1/LO1 register. */ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { - if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) { - /* Treat as NOP. */ - return; - } - switch (opc) { case MMI_OPC_MFHI1: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); + gen_store_gpr(cpu_HI[1], reg); break; case MMI_OPC_MFLO1: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); + gen_store_gpr(cpu_LO[1], reg); break; case MMI_OPC_MTHI1: - if (reg != 0) { - tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); - } else { - tcg_gen_movi_tl(cpu_HI[1], 0); - } + gen_load_gpr(cpu_HI[1], reg); break; case MMI_OPC_MTLO1: - if (reg != 0) { - tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); - } else { - tcg_gen_movi_tl(cpu_LO[1], 0); - } + gen_load_gpr(cpu_LO[1], reg); break; default: MIPS_INVAL("mfthilo1 TX79"); |