diff options
| author | Frédéric Pétrot | 2022-01-06 22:00:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | fc313c64345453c7a668d765610dfd7135e21a98 (patch) | |
| tree | 336a2b0e28691f2333931bf366f85e70e60f3091 /target/riscv/insn_trans/trans_rvi.c.inc | |
| parent | target/riscv: Fix position of 'experimental' comment (diff) | |
| download | qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.gz qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.xz qemu-fc313c64345453c7a668d765610dfd7135e21a98.zip | |
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvi.c.inc')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index e51dbc41c5..4a2aefe3a5 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -216,13 +216,13 @@ static bool trans_lwu(DisasContext *ctx, arg_lwu *a) static bool trans_ld(DisasContext *ctx, arg_ld *a) { REQUIRE_64BIT(ctx); - return gen_load(ctx, a, MO_TEQ); + return gen_load(ctx, a, MO_TEUQ); } static bool trans_sd(DisasContext *ctx, arg_sd *a) { REQUIRE_64BIT(ctx); - return gen_store(ctx, a, MO_TEQ); + return gen_store(ctx, a, MO_TEUQ); } static bool trans_addi(DisasContext *ctx, arg_addi *a) |