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path: root/target/riscv/insn_trans/trans_rvi.c.inc
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Add Zihintpause supportDao Lu2022-09-071-0/+16
* target/riscv: Minimize the calls to decode_save_opcRichard Henderson2022-07-031-0/+2
* target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo2022-07-031-6/+2Star
* target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich2022-02-161-1/+1
* target/riscv: Calculate address according to XLENLIU Zhiwei2022-01-211-16/+2Star
* target/riscv: Adjust csr write mask with XLENLIU Zhiwei2022-01-211-4/+8
* target/riscv: Sign extend pc for different XLENLIU Zhiwei2022-01-211-2/+3
* target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2022-01-211-3/+1Star
* target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot2022-01-081-43/+158
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-081-14/+145
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-081-18/+206
* target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2022-01-081-4/+4
* target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot2022-01-081-6/+94
* target/riscv: moving some insns close to similar insnsFrédéric Pétrot2022-01-081-17/+17
* target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2022-01-081-6/+6
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-2/+2
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-281-0/+2
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-221-12/+14
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-211-9/+9
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-161-5/+3Star
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-011-52/+122
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-011-70/+18Star
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-011-17/+22
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-22/+22
* target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-081-50/+4Star
* target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-111-0/+6
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-4/+12
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+577
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