diff options
| author | Alistair Francis | 2022-06-08 08:14:37 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-06-10 01:31:43 +0200 |
| commit | 26b2bc58599c02b35e55afbd1bd050faa3d187c2 (patch) | |
| tree | a8dc37062cb08473fe68658fa17263f673a9a001 /target/riscv/insn_trans | |
| parent | target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti... (diff) | |
| download | qemu-26b2bc58599c02b35e55afbd1bd050faa3d187c2.tar.gz qemu-26b2bc58599c02b35e55afbd1bd050faa3d187c2.tar.xz qemu-26b2bc58599c02b35e55afbd1bd050faa3d187c2.zip | |
target/riscv: Don't expose the CPU properties on names CPUs
There are currently two types of RISC-V CPUs:
- Generic CPUs (base or any) that allow complete custimisation
- "Named" CPUs that match existing hardware
Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.
We originally exposed these as part of the named CPUs as well, but that was
by accident.
Exposing the CPU properties to named CPUs means that we accidently
enable extensions that don't exist on the CPUs by default. For example
the SiFive E CPU currently support the zba extension, which is a bug.
This patch instead only exposes the CPU extensions to the generic CPUs.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
0 files changed, 0 insertions, 0 deletions