diff options
| author | Dao Lu | 2022-07-25 05:47:28 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-07 09:18:33 +0200 |
| commit | 4696f0ab5c436ed53567ce6baec67c921d9b70ae (patch) | |
| tree | 435b5069b3fb5f03bff74765763330893bc84f10 /target/riscv/insn_trans | |
| parent | target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti... (diff) | |
| download | qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.tar.gz qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.tar.xz qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.zip | |
target/riscv: Add Zihintpause support
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ca8e3d1ea1..c49dbec0eb 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -792,6 +792,22 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a) return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL); } +static bool trans_pause(DisasContext *ctx, arg_pause *a) +{ + if (!ctx->cfg_ptr->ext_zihintpause) { + return false; + } + + /* + * PAUSE is a no-op in QEMU, + * end the TB and return to main loop + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + + return true; +} static bool trans_fence(DisasContext *ctx, arg_fence *a) { |