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| author | Frank Chang | 2021-12-10 08:56:37 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:53:31 +0100 |
| commit | 8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc (patch) | |
| tree | ee8261b39a8e68d9fde178ede5a888b81784a05c /target/riscv/insn_trans | |
| parent | target/riscv: rvv-1.0: slide instructions (diff) | |
| download | qemu-8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc.tar.gz qemu-8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc.tar.xz qemu-8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc.zip | |
target/riscv: rvv-1.0: floating-point slide instructions
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-52-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5c0c3d2547..597a367444 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3121,6 +3121,22 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) +/* Vector Floating-Point Slide Instructions */ +static bool fslideup_check(DisasContext *s, arg_rmrr *a) +{ + return slideup_check(s, a) && + require_rvf(s); +} + +static bool fslidedown_check(DisasContext *s, arg_rmrr *a) +{ + return slidedown_check(s, a) && + require_rvf(s); +} + +GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check) +GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check) + /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { |