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author | Bastian Koppelmann | 2019-02-13 16:54:07 +0100 |
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committer | Bastian Koppelmann | 2019-03-13 10:40:50 +0100 |
commit | 8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3 (patch) | |
tree | cb5f040ade5d27ff897f946b7ff321ace0fc89a3 /target/riscv/insn_trans | |
parent | target/riscv: Remove manual decoding of RV32/64M insn (diff) | |
download | qemu-8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3.tar.gz qemu-8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3.tar.xz qemu-8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3.zip |
target/riscv: Rename trans_arith to gen_arith
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/riscv/insn_trans')
-rw-r--r-- | target/riscv/insn_trans/trans_rvi.inc.c | 18 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvm.inc.c | 14 |
2 files changed, 16 insertions, 16 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 88ef0003ec..d420a4d8b2 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) static bool trans_add(DisasContext *ctx, arg_add *a) { - return trans_arith(ctx, a, &tcg_gen_add_tl); + return gen_arith(ctx, a, &tcg_gen_add_tl); } static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return trans_arith(ctx, a, &tcg_gen_sub_tl); + return gen_arith(ctx, a, &tcg_gen_sub_tl); } static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return trans_arith(ctx, a, &gen_slt); + return gen_arith(ctx, a, &gen_slt); } static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return trans_arith(ctx, a, &gen_sltu); + return gen_arith(ctx, a, &gen_sltu); } static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return trans_arith(ctx, a, &tcg_gen_xor_tl); + return gen_arith(ctx, a, &tcg_gen_xor_tl); } static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) static bool trans_or(DisasContext *ctx, arg_or *a) { - return trans_arith(ctx, a, &tcg_gen_or_tl); + return gen_arith(ctx, a, &tcg_gen_or_tl); } static bool trans_and(DisasContext *ctx, arg_and *a) { - return trans_arith(ctx, a, &tcg_gen_and_tl); + return gen_arith(ctx, a, &tcg_gen_and_tl); } #ifdef TARGET_RISCV64 @@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) static bool trans_addw(DisasContext *ctx, arg_addw *a) { - return trans_arith(ctx, a, &gen_addw); + return gen_arith(ctx, a, &gen_addw); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { - return trans_arith(ctx, a, &gen_subw); + return gen_arith(ctx, a, &gen_subw); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index d2bf2f1719..204af225f8 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -22,7 +22,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &tcg_gen_mul_tl); + return gen_arith(ctx, a, &tcg_gen_mul_tl); } static bool trans_mulh(DisasContext *ctx, arg_mulh *a) @@ -44,7 +44,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_mulhsu); + return gen_arith(ctx, a, &gen_mulhsu); } static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -66,32 +66,32 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_div); + return gen_arith(ctx, a, &gen_div); } static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_divu); + return gen_arith(ctx, a, &gen_divu); } static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_rem); + return gen_arith(ctx, a, &gen_rem); } static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_remu); + return gen_arith(ctx, a, &gen_remu); } #ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_EXT(ctx, RVM); - return trans_arith(ctx, a, &gen_mulw); + return gen_arith(ctx, a, &gen_mulw); } static bool trans_divw(DisasContext *ctx, arg_divw *a) |