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| author | Philippe Mathieu-Daudé | 2019-07-23 14:08:15 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:42 +0200 |
| commit | 0b84b6629d444ac31de33fb3125cb3e19740d766 (patch) | |
| tree | bbdef0e3b2b3bb92ab40ded5d19b66132781c760 /target/riscv | |
| parent | riscv: sifive_u: Fix clock-names property for ethernet node (diff) | |
| download | qemu-0b84b6629d444ac31de33fb3125cb3e19740d766.tar.gz qemu-0b84b6629d444ac31de33fb3125cb3e19740d766.tar.xz qemu-0b84b6629d444ac31de33fb3125cb3e19740d766.zip | |
target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/Makefile.objs | 3 | ||||
| -rw-r--r-- | target/riscv/pmp.c | 4 |
2 files changed, 2 insertions, 5 deletions
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc1d1..b754e4bf32 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,5 @@ -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o +obj-$(CONFIG_SOFTMMU) += pmp.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 958c7502a0..d836288cb4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,8 +28,6 @@ #include "qapi/error.h" #include "cpu.h" -#ifndef CONFIG_USER_ONLY - #define RISCV_DEBUG_PMP 0 #define PMP_DEBUG(fmt, ...) \ do { \ @@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) return 0; } } - -#endif |