diff options
| author | Alistair Francis | 2019-04-20 04:27:02 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:24 +0200 |
| commit | 16fdb8ff64374ed51b246437e13043039a8eb9f9 (patch) | |
| tree | 5afac00fc51a01dbc66daf0f318516126c38d2cb /target/riscv | |
| parent | target/riscv: Trigger interrupt on MIP update asynchronously (diff) | |
| download | qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.tar.gz qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.tar.xz qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.zip | |
target/riscv: Improve the scause logic
No functional change, just making the code easier to read.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7318da289f..c577a262b8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -515,7 +515,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); env->mstatus = s; - env->scause = cause | ~(((target_ulong)-1) >> async); + env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); env->sepc = env->pc; env->sbadaddr = tval; env->pc = (env->stvec >> 2 << 2) + |