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| author | Frank Chang | 2020-07-10 12:48:16 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-14 02:25:37 +0200 |
| commit | 1989205c4e973bc7f9fac0ce0700993f30582538 (patch) | |
| tree | 7019f97dd872ea4db7bf69fe38a0a1d400fffb00 /target/riscv | |
| parent | target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion (diff) | |
| download | qemu-1989205c4e973bc7f9fac0ce0700993f30582538.tar.gz qemu-1989205c4e973bc7f9fac0ce0700993f30582538.tar.xz qemu-1989205c4e973bc7f9fac0ce0700993f30582538.zip | |
target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 433cdacbe1..7cd08f0868 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_vec_sub8_i64(d, b, a); + tcg_gen_vec_sub16_i64(d, b, a); } static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |