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| author | Frank Chang | 2022-01-18 02:45:20 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:56 +0100 |
| commit | 2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9 (patch) | |
| tree | 99c9e4eb926d7783a5a9459ff26a52a90422a0d1 /target/riscv | |
| parent | target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns (diff) | |
| download | qemu-2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9.tar.gz qemu-2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9.tar.xz qemu-2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9.zip | |
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ef269378de..c2b570e904 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -688,6 +688,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), |