diff options
| author | Anup Patel | 2022-02-04 18:46:42 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-02-16 03:24:18 +0100 |
| commit | 32b0ada038629311aa90499a68de29473df7935d (patch) | |
| tree | 6c0e8aecc592dcbf74cc40c9b128dc3385d46ca0 /target/riscv | |
| parent | target/riscv: Allow setting CPU feature from machine/device emulation (diff) | |
| download | qemu-32b0ada038629311aa90499a68de29473df7935d.tar.gz qemu-32b0ada038629311aa90499a68de29473df7935d.tar.xz qemu-32b0ada038629311aa90499a68de29473df7935d.zip | |
target/riscv: Add AIA cpu feature
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 283a3cda4b..8838c61ae4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -78,7 +78,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_AIA }; #define PRIV_VERSION_1_10_0 0x00011000 |