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| author | Alistair Francis | 2019-10-03 18:59:29 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-10-28 16:46:06 +0100 |
| commit | 3aa9004f09c80290e119cd7b93dfca73ab418883 (patch) | |
| tree | 5df914d7ad2dacbc13a0b9d7973eb75c2778b16d /target/riscv | |
| parent | target/riscv: Make the priv register writable by GDB (diff) | |
| download | qemu-3aa9004f09c80290e119cd7b93dfca73ab418883.tar.gz qemu-3aa9004f09c80290e119cd7b93dfca73ab418883.tar.xz qemu-3aa9004f09c80290e119cd7b93dfca73ab418883.zip | |
riscv/boot: Fix possible memory leak
Coverity (CID 1405786) thinks that there is a possible memory leak as
we don't guarantee that the memory allocated from riscv_find_firmware()
is freed. This is a false positive, but let's tidy up the code to fix
the warning.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
0 files changed, 0 insertions, 0 deletions