diff options
| author | Xinhao Zhang | 2020-10-30 01:48:15 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | 422819776101520cb56658ee5facf926526cf870 (patch) | |
| tree | 99923b17aaa46c636658b84a17c5138e8e875b59 /target/riscv | |
| parent | hw/riscv: microchip_pfsoc: Hook the I2C1 controller (diff) | |
| download | qemu-422819776101520cb56658ee5facf926526cf870.tar.gz qemu-422819776101520cb56658ee5facf926526cf870.tar.xz qemu-422819776101520cb56658ee5facf926526cf870.zip | |
target/riscv/csr.c : add space before the open parenthesis '('
Fix code style. Space required before the open parenthesis '('.
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reported-by: Euler Robot <euler.robot@huawei.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e33f6cdc11..93263f8e06 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -882,7 +882,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { return -RISCV_EXCP_ILLEGAL_INST; } else { - if((val ^ env->satp) & SATP_ASID) { + if ((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); } env->satp = val; |