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| author | Peter Maydell | 2019-08-19 16:58:01 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-08-19 16:58:01 +0200 |
| commit | 50d69ee0d82378c7c21f482492dacfe0916b4863 (patch) | |
| tree | d63314314e86a387ba2de6ba9799c96f5fe4156d /target/riscv | |
| parent | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-08-1... (diff) | |
| parent | targets (various): use softfloat-helpers.h where we can (diff) | |
| download | qemu-50d69ee0d82378c7c21f482492dacfe0916b4863.tar.gz qemu-50d69ee0d82378c7c21f482492dacfe0916b4863.tar.xz qemu-50d69ee0d82378c7c21f482492dacfe0916b4863.zip | |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-softfloat-headers-190819-1' into staging
Softfloat updates
- minor refactoring of constants
- drop LIT64 macro
- re-organise header inclusion
# gpg: Signature made Mon 19 Aug 2019 12:08:37 BST
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-softfloat-headers-190819-1:
targets (various): use softfloat-helpers.h where we can
target/riscv: rationalise softfloat includes
target/mips: rationalise softfloat includes
fpu: rename softfloat-specialize.h -> .inc.c
fpu: make softfloat-macros "self-contained"
fpu: move inline helpers into a separate header
fpu: remove the LIT64 macro
target/m68k: replace LIT64 with UINT64_C macros
fpu: replace LIT64 with UINT64_C macros
fpu: use min/max values from stdint.h for integral overflow
fpu: convert float[16/32/64]_squash_denormal to new modern style
fpu: replace LIT64 usage with UINT64_C for specialize constants
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 1 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/fpu_helper.c | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8d07bd20a..6d52f97d7c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "fpu/softfloat-helpers.h" /* RISC-V CPU definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..240b31e2eb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -22,7 +22,7 @@ #include "qom/cpu.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" +#include "fpu/softfloat-types.h" #define TCG_GUEST_DEFAULT_MO 0 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index b4f818a646..0b79562a69 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -21,6 +21,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" target_ulong riscv_cpu_get_fflags(CPURISCVState *env) { |