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| author | Rahul Pathak | 2022-08-24 16:52:55 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-26 23:04:38 +0200 |
| commit | 513eb437aef7687ad1963d935ffb884fff3c4775 (patch) | |
| tree | 824a85ca54a06bdfd2cfaf2067ca10e6f58fe8e7 /target/riscv | |
| parent | docs/system: clean up code escape for riscv virt platform (diff) | |
| download | qemu-513eb437aef7687ad1963d935ffb884fff3c4775.tar.gz qemu-513eb437aef7687ad1963d935ffb884fff3c4775.tar.xz qemu-513eb437aef7687ad1963d935ffb884fff3c4775.zip | |
target/riscv: Remove sideleg and sedeleg
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7be12cac2e..b762807e4e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -190,8 +190,6 @@ /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 |