diff options
| author | Alistair Francis | 2020-08-12 21:13:36 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-08-25 18:11:36 +0200 |
| commit | 543ba53157f9003eaa9b802d44c577c5814e232c (patch) | |
| tree | c61941d67870f4763020fcc3fb7720b9529ccadb /target/riscv | |
| parent | target/riscv: Update the Hypervisor trap return/entry (diff) | |
| download | qemu-543ba53157f9003eaa9b802d44c577c5814e232c.tar.gz qemu-543ba53157f9003eaa9b802d44c577c5814e232c.tar.xz qemu-543ba53157f9003eaa9b802d44c577c5814e232c.zip | |
target/riscv: Update the CSRs to the v0.6 Hyp extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fb6a3e9092..573d85da41 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -437,15 +437,17 @@ #endif /* hstatus CSR bits */ -#define HSTATUS_SPRV 0x00000001 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_GVA 0x00000040 #define HSTATUS_SPV 0x00000080 -#define HSTATUS_SP2P 0x00000100 -#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_SPVP 0x00000100 +#if defined(TARGET_RISCV64) +#define HSTATUS_VSXL 0x300000000 +#endif #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL |