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| author | Alistair Francis | 2020-12-16 19:22:26 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:43 +0100 |
| commit | 617448a46b60c353fae0c645a024b628c1f9f700 (patch) | |
| tree | 9a9ba6c916e9e59a6448f94c880902e373cb2f6d /target/riscv | |
| parent | intc/ibex_plic: Clear interrupts that occur during claim process (diff) | |
| download | qemu-617448a46b60c353fae0c645a024b628c1f9f700.tar.gz qemu-617448a46b60c353fae0c645a024b628c1f9f700.tar.xz qemu-617448a46b60c353fae0c645a024b628c1f9f700.zip | |
hw/riscv: Expand the is 32-bit check to support more CPUs
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
0 files changed, 0 insertions, 0 deletions