diff options
| author | Alistair Francis | 2019-04-20 04:27:26 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:24 +0200 |
| commit | 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2 (patch) | |
| tree | 8019927aac73fad6576f765013ee38df7c6f8c00 /target/riscv | |
| parent | target/riscv: Allow setting mstatus virtulisation bits (diff) | |
| download | qemu-71f09a5bb48d0c51b87e70158407ec2db4a9c6e2.tar.gz qemu-71f09a5bb48d0c51b87e70158407ec2db4a9c6e2.tar.xz qemu-71f09a5bb48d0c51b87e70158407ec2db4a9c6e2.zip | |
target/riscv: Add Hypervisor CSR macros
Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fe7164754b..52c2169977 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,12 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 +/* Hpervisor CSRs */ +#define CSR_HSTATUS 0xa00 +#define CSR_HEDELEG 0xa02 +#define CSR_HIDELEG 0xa03 +#define CSR_HGATP 0xa80 + /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 @@ -292,9 +298,6 @@ #define CSR_MHPMCOUNTER31H 0xb9f /* Legacy Hypervisor Trap Setup (priv v1.9.1) */ -#define CSR_HSTATUS 0x200 -#define CSR_HEDELEG 0x202 -#define CSR_HIDELEG 0x203 #define CSR_HIE 0x204 #define CSR_HTVEC 0x205 |