diff options
| author | Alistair Francis | 2020-08-12 21:13:30 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-08-25 18:11:36 +0200 |
| commit | 84b1c04bbaf48798a535b38410a0bf839f4a1943 (patch) | |
| tree | 6b2d2c7f29bc834e39c8b60fc36158bd53adec63 /target/riscv | |
| parent | target/riscv: Convert MSTATUS MTL to GVA (diff) | |
| download | qemu-84b1c04bbaf48798a535b38410a0bf839f4a1943.tar.gz qemu-84b1c04bbaf48798a535b38410a0bf839f4a1943.tar.xz qemu-84b1c04bbaf48798a535b38410a0bf839f4a1943.zip | |
target/riscv: Fix the interrupt cause code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_helper.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0b4ad4bf46..661e790fdc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -916,14 +916,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt * no if hypervisor has delegated one of hs mode's interrupt */ if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || - cause == IRQ_VS_EXT) + cause == IRQ_VS_EXT) { cause = cause - 1; - /* Trap to VS mode */ + } env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ |