diff options
| author | Michael Clark | 2019-03-16 02:21:12 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-03-19 13:14:40 +0100 |
| commit | 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7 (patch) | |
| tree | 3befad4f4f5aebdc43c661520c5b330b67bc9533 /target/riscv | |
| parent | RISC-V: Add support for vectored interrupts (diff) | |
| download | qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.tar.gz qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.tar.xz qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.zip | |
RISC-V: Convert trap debugging to trace events
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_helper.c | 12 | ||||
| -rw-r--r-- | target/riscv/trace-events | 2 |
2 files changed, 5 insertions, 9 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a02f4dad8c..6d3fbc3401 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,8 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" - -#define RISCV_DEBUG_INTERRUPT 0 +#include "trace.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } - if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, " - "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n", - env->mhartid, async ? "intr" : "trap", - (async ? riscv_intr_names : riscv_excp_names)[cause], - env->pc, tval); - } + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? + (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { diff --git a/target/riscv/trace-events b/target/riscv/trace-events new file mode 100644 index 0000000000..48af0373df --- /dev/null +++ b/target/riscv/trace-events @@ -0,0 +1,2 @@ +# target/riscv/cpu_helper.c +riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" |