diff options
| author | Alistair Francis | 2022-06-30 01:31:01 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-07-03 02:03:20 +0200 |
| commit | b509caceaa6dcb694015390a202002a0f3088ad0 (patch) | |
| tree | 61bbb69ae81bd03b7726bb9874fb7cc78bef65fc /target/riscv | |
| parent | target/riscv: Support mcycle/minstret write operation (diff) | |
| download | qemu-b509caceaa6dcb694015390a202002a0f3088ad0.tar.gz qemu-b509caceaa6dcb694015390a202002a0f3088ad0.tar.xz qemu-b509caceaa6dcb694015390a202002a0f3088ad0.zip | |
target/riscv: Fixup MSECCFG minimum priv check
There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d65318dcc6..d14a0cb0a0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3812,7 +3812,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Physical Memory Protection */ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, |