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| author | Jonathan Behrens | 2019-04-01 21:12:07 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:19 +0200 |
| commit | b86f4167630802128d94f3c89043d97d2f4c2546 (patch) | |
| tree | a91a1a53139219ad5e3295bbf7df78327d08d908 /target/riscv | |
| parent | SiFive RISC-V GPIO Device (diff) | |
| download | qemu-b86f4167630802128d94f3c89043d97d2f4c2546.tar.gz qemu-b86f4167630802128d94f3c89043d97d2f4c2546.tar.xz qemu-b86f4167630802128d94f3c89043d97d2f4c2546.zip | |
target/riscv: Do not allow sfence.vma from user mode
The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.
Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/op_helper.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b7dc18a41e..644d0fb35f 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env) { RISCVCPU *cpu = riscv_env_get_cpu(env); CPUState *cs = CPU(cpu); - if (env->priv == PRV_S && - env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TVM)) { + if (!(env->priv >= PRV_S) || + (env->priv == PRV_S && + env->priv_ver >= PRIV_VERSION_1_10_0 && + get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { tlb_flush(cs); |