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| author | Philippe Mathieu-Daudé | 2021-05-16 22:53:33 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-06-08 01:59:43 +0200 |
| commit | bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3 (patch) | |
| tree | cf7fbd7bc18d759bc07a14474587e96c92467041 /target/riscv | |
| parent | docs/system: Move the RISC-V -bios information to removed (diff) | |
| download | qemu-bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3.tar.gz qemu-bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3.tar.xz qemu-bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3.zip | |
target/riscv: Do not include 'pmp.h' in user emulation
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210516205333.696094-1-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7e879fb9ca..0619b491a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,7 +97,9 @@ enum { typedef struct CPURISCVState CPURISCVState; +#if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#endif #define RV_VLEN_MAX 256 |