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| author | Alexandre Mergnat | 2020-07-06 10:45:50 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-14 02:25:37 +0200 |
| commit | cfad709bceb629a4ebeb5d8a3acd1871b9a6436b (patch) | |
| tree | ecd23f58326ceec05471513539a5378ef980332b /target/riscv | |
| parent | tcg/riscv: Remove superfluous breaks (diff) | |
| download | qemu-cfad709bceb629a4ebeb5d8a3acd1871b9a6436b.tar.gz qemu-cfad709bceb629a4ebeb5d8a3acd1871b9a6436b.tar.xz qemu-cfad709bceb629a4ebeb5d8a3acd1871b9a6436b.zip | |
target/riscv: Fix pmp NA4 implementation
The end address calculation for NA4 mode is wrong because the address
used isn't shifted.
It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.
The solution is to use the shifted address calculated for start address
variable.
Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200706084550.24117-1-amergnat@baylibre.com
Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
[ Changes by AF:
- Improve the commit title and message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/pmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9418660f1b..2a2b9f5363 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -171,7 +171,7 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) case PMP_AMATCH_NA4: sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ - ea = (this_addr + 4u) - 1u; + ea = (sa + 4u) - 1u; break; case PMP_AMATCH_NAPOT: |