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| author | Hesham Almatary | 2019-05-30 15:51:30 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-24 08:44:41 +0200 |
| commit | e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace (patch) | |
| tree | 028d6cd225c50f0d1335ab0eae718e143bf6b7ed /target/riscv | |
| parent | target/riscv: Implement riscv_cpu_unassigned_access (diff) | |
| download | qemu-e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace.tar.gz qemu-e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace.tar.xz qemu-e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace.zip | |
RISC-V: Only Check PMP if MMU translation succeeds
The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.
For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.
Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_helper.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0bbfb7f48b..a45b05ef83 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -436,6 +436,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, " prot %d\n", __func__, address, ret, pa, prot); if (riscv_feature(env, RISCV_FEATURE_PMP) && + (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret = TRANSLATE_FAIL; } |