diff options
| author | Richard Henderson | 2019-04-01 05:11:48 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:22 +0200 |
| commit | e761799796ac2211b9706753c459e117e7be58fa (patch) | |
| tree | 604829a8b4625c20c8ef760ef708f215be7c92fc /target/riscv | |
| parent | RISC-V: fix single stepping over ret and other branching instructions (diff) | |
| download | qemu-e761799796ac2211b9706753c459e117e7be58fa.tar.gz qemu-e761799796ac2211b9706753c459e117e7be58fa.tar.xz qemu-e761799796ac2211b9706753c459e117e7be58fa.zip | |
target/riscv: Name the argument sets for all of insn32 formats
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn32.decode | 10 | ||||
| -rw-r--r-- | target/riscv/translate.c | 18 |
2 files changed, 25 insertions, 3 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f3ab7aa52..77f794ed70 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -34,9 +34,13 @@ %imm_u 12:s20 !function=ex_shift_12 # Argument sets: +&empty &b imm rs2 rs1 &i imm rs1 rd +&j imm rd &r rd rs1 rs2 +&s imm rs1 rs2 +&u imm rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd @@ -44,9 +48,9 @@ @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 -@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 -@u .................... ..... ....... imm=%imm_u %rd -@j .................... ..... ....... imm=%imm_j %rd +@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 +@u .................... ..... ....... &u imm=%imm_u %rd +@j .................... ..... ....... &j imm=%imm_j %rd @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd @csr ............ ..... ... ..... ....... %csr %rs1 %rd diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 840ecbef36..928374242e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -687,11 +687,29 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" +/* + * Auto-generated decoder. + * Note that the 16-bit decoder reuses some of the trans_* functions + * initially declared by the 32-bit decoder, which results in duplicate + * declaration warnings. Suppress them. + */ +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wredundant-decls" +# ifdef __clang__ +# pragma GCC diagnostic ignored "-Wtypedef-redefinition" +# endif +#endif + bool decode_insn16(DisasContext *ctx, uint16_t insn); /* auto-generated decoder*/ #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic pop +#endif + static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ |