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| author | LIU Zhiwei | 2022-01-20 13:20:50 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:57 +0100 |
| commit | f297245f6a780f496fb171af6fcd21ff3e6783c3 (patch) | |
| tree | 4cfbf3189ca73a5e5372f3b032a3d4cbcb59dd1f /target/riscv | |
| parent | target/riscv: Enable uxl field write (diff) | |
| download | qemu-f297245f6a780f496fb171af6fcd21ff3e6783c3.tar.gz qemu-f297245f6a780f496fb171af6fcd21ff3e6783c3.tar.xz qemu-f297245f6a780f496fb171af6fcd21ff3e6783c3.zip | |
target/riscv: Relax UXL field for debugging
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 523d07a95e..e5f9d4ef93 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -584,7 +584,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW | MSTATUS_VS; - if (xl != MXL_RV32) { + if (xl != MXL_RV32 || env->debugger) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -900,7 +900,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, { uint64_t mask = sstatus_v1_10_mask; uint64_t sstatus = env->mstatus & mask; - if (env->xl != MXL_RV32) { + if (env->xl != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } @@ -912,7 +912,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask = (sstatus_v1_10_mask); - if (env->xl != MXL_RV32) { + if (env->xl != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } /* TODO: Use SXL not MXL. */ @@ -925,7 +925,7 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (env->xl != MXL_RV32) { + if (env->xl != MXL_RV32 || env->debugger) { if ((val & SSTATUS64_UXL) != 0) { mask |= SSTATUS64_UXL; } |