diff options
| author | Emmanuel Blot | 2021-04-16 16:17:11 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:07 +0200 |
| commit | f9e580c13ae0d42cf8989063254300c59166ffed (patch) | |
| tree | b8ecfb4bbf3ccb3895a4d04c83deb0131877200d /target/riscv | |
| parent | target/riscv: fix vrgather macro index variable type bug (diff) | |
| download | qemu-f9e580c13ae0d42cf8989063254300c59166ffed.tar.gz qemu-f9e580c13ae0d42cf8989063254300c59166ffed.tar.xz qemu-f9e580c13ae0d42cf8989063254300c59166ffed.zip | |
target/riscv: fix exception index on instruction access fault
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_helper.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 659ca8a173..1018c0036d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type == MMU_DATA_LOAD) { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; } env->badaddr = addr; |