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| author | Max Filippov | 2011-11-26 12:48:41 +0100 |
|---|---|---|
| committer | Max Filippov | 2017-01-17 04:19:03 +0100 |
| commit | 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (patch) | |
| tree | d64a088bd5188f6b19fe1fcd341283140f5fcc0e /target/xtensa/translate.c | |
| parent | target/xtensa: tests: clean up interrupt tests (diff) | |
| download | qemu-3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02.tar.gz qemu-3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02.tar.xz qemu-3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02.zip | |
target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/translate.c')
| -rw-r--r-- | target/xtensa/translate.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index c541b59747..c0408a01c7 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1420,11 +1420,19 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 6: /*RER*/ - TBD(); + HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { + gen_helper_rer(cpu_R[RRR_T], cpu_env, cpu_R[RRR_S]); + } break; case 7: /*WER*/ - TBD(); + HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { + gen_helper_wer(cpu_env, cpu_R[RRR_T], cpu_R[RRR_S]); + } break; case 8: /*ROTWw*/ |