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authorPeter Maydell2018-05-18 19:25:29 +0200
committerPeter Maydell2018-05-18 19:25:29 +0200
commit5bcf917ee37a5efbef99f091a96db54a5276becb (patch)
tree46b15d3b22e7121f4db061104c335ba2de6533be /target/xtensa/translate.c
parentMerge remote-tracking branch 'remotes/famz/tags/docker-and-block-pull-request... (diff)
parenttarget/arm: Implement SVE Permute - Extract Group (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180518' into staging
target-arm queue: * Initial part of SVE implementation (currently disabled) * smmuv3: fix some minor Coverity issues * add model of Xilinx ZynqMP generic DMA controller * expose (most) Arm coprocessor/system registers to gdb via QEMU's gdbstub, for reads only # gpg: Signature made Fri 18 May 2018 18:18:27 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180518: (32 commits) target/arm: Implement SVE Permute - Extract Group target/arm: Implement SVE Integer Wide Immediate - Predicated Group target/arm: Implement SVE Bitwise Immediate Group target/arm: Implement SVE Element Count Group target/arm: Implement SVE floating-point trig select coefficient target/arm: Implement SVE floating-point exponential accelerator target/arm: Implement SVE Compute Vector Address Group target/arm: Implement SVE Bitwise Shift - Unpredicated Group target/arm: Implement SVE Stack Allocation Group target/arm: Implement SVE Index Generation Group target/arm: Implement SVE Integer Arithmetic - Unpredicated Group target/arm: Implement SVE Integer Multiply-Add Group target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group target/arm: Implement SVE bitwise shift by wide elements (predicated) target/arm: Implement SVE bitwise shift by vector (predicated) target/arm: Implement SVE bitwise shift by immediate (predicated) target/arm: Implement SVE Integer Reduction Group target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group target/arm: Implement SVE Predicate Misc Group target/arm: Implement SVE Predicate Logical Operations Group ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/xtensa/translate.c')
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