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| author | Max Filippov | 2016-11-12 07:40:18 +0100 |
|---|---|---|
| committer | Max Filippov | 2017-01-15 22:01:56 +0100 |
| commit | 9e03ade4411c81a7f7d974dcedf0390835ce4096 (patch) | |
| tree | 5ed7163044ac610d041277e20def7990e507b1b5 /target/xtensa/translate.c | |
| parent | target/xtensa: fix ICACHE/DCACHE options detection (diff) | |
| download | qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.tar.gz qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.tar.xz qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.zip | |
target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/translate.c')
| -rw-r--r-- | target/xtensa/translate.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 7a198fa203..c541b59747 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -133,6 +133,7 @@ static const XtensaReg sregnames[256] = { [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), + [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), @@ -637,6 +638,12 @@ static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) return true; } +static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) +{ + gen_helper_wsr_memctl(cpu_env, v); + return false; +} + static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); @@ -821,6 +828,7 @@ static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) [ITLBCFG] = gen_wsr_tlbcfg, [DTLBCFG] = gen_wsr_tlbcfg, [IBREAKENABLE] = gen_wsr_ibreakenable, + [MEMCTL] = gen_wsr_memctl, [ATOMCTL] = gen_wsr_atomctl, [IBREAKA] = gen_wsr_ibreaka, [IBREAKA + 1] = gen_wsr_ibreaka, |