diff options
| author | Philippe Mathieu-Daudé | 2020-12-02 18:49:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2020-12-13 20:26:02 +0100 |
| commit | 17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3 (patch) | |
| tree | cd5bd83fc8738fae872942478003ac6baf5e7f4c /target | |
| parent | target/mips: Remove mips_def_t unused argument from mvp_init() (diff) | |
| download | qemu-17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3.tar.gz qemu-17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3.tar.xz qemu-17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3.zip | |
target/mips: Introduce ase_mt_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'Multi-Threading Present' bit, introduce an helper
to simplify code review.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/cp0_helper.c | 2 | ||||
| -rw-r--r-- | target/mips/cpu.c | 2 | ||||
| -rw-r--r-- | target/mips/cpu.h | 7 | ||||
| -rw-r--r-- | target/mips/helper.c | 2 | ||||
| -rw-r--r-- | target/mips/translate.c | 2 |
5 files changed, 11 insertions, 4 deletions
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index cb899fe3d7..36a92857bf 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1164,7 +1164,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) old = env->CP0_EntryHi; val = (arg1 & mask) | (old & ~mask); env->CP0_EntryHi = val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 687e2680dd..9d7edc1ca2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { /* * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5d3b2a01c0..3ac21d0e9c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ diff --git a/target/mips/helper.c b/target/mips/helper.c index 59de58fcbc..0c65786579 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) tlb_flush(env_cpu(env)); } #endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f218997f04..ccc82abce0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31917,7 +31917,7 @@ void cpu_state_reset(CPUMIPSState *env) cpu_mips_store_count(env, 1); - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { int i; /* Only TC0 on VPE 0 starts as active. */ |