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| author | Artyom Tarasenko | 2016-06-12 22:19:43 +0200 |
|---|---|---|
| committer | Artyom Tarasenko | 2017-01-18 22:03:44 +0100 |
| commit | 1a2aefae6627170fdee689b394a65f76080c068a (patch) | |
| tree | 5bb295468da350647ab92170f246f8200e9956ac /target | |
| parent | target-sparc: add UltraSPARC T1 TLB #defines (diff) | |
| download | qemu-1a2aefae6627170fdee689b394a65f76080c068a.tar.gz qemu-1a2aefae6627170fdee689b394a65f76080c068a.tar.xz qemu-1a2aefae6627170fdee689b394a65f76080c068a.zip | |
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode and
PSTATE.ie = 1. At all other times, they are held pending.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sparc/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f65d8b5c1e..21fe0d1d3e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -736,8 +736,9 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1) if (env1->psret != 0) return 1; #else - if (env1->pstate & PS_IE) + if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { return 1; + } #endif return 0; |