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| author | Laurent Vivier | 2017-01-13 19:36:31 +0100 |
|---|---|---|
| committer | Laurent Vivier | 2017-01-14 10:06:21 +0100 |
| commit | 308feb935249ad745ef763707e1db69bc10ba789 (patch) | |
| tree | 4afbef88fa8aa4dc1ddd76213e145cd77f136983 /target | |
| parent | target-m68k: fix gen_flush_flags() (diff) | |
| download | qemu-308feb935249ad745ef763707e1db69bc10ba789.tar.gz qemu-308feb935249ad745ef763707e1db69bc10ba789.tar.xz qemu-308feb935249ad745ef763707e1db69bc10ba789.zip | |
target-m68k: manage pre-dec et post-inc in CAS
In these cases we must update the address register after
the operation.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
Diffstat (limited to 'target')
| -rw-r--r-- | target/m68k/translate.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0e97900b2c..23e2b06205 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1963,6 +1963,15 @@ DISAS_INSN(cas) gen_partset_reg(opsize, DREG(ext, 0), load); tcg_temp_free(load); + + switch (extract32(insn, 3, 3)) { + case 3: /* Indirect postincrement. */ + tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize)); + break; + case 4: /* Indirect predecrememnt. */ + tcg_gen_mov_i32(AREG(insn, 0), addr); + break; + } } DISAS_INSN(cas2w) |