diff options
| author | Sven Schnelle | 2019-03-11 20:15:52 +0100 |
|---|---|---|
| committer | Richard Henderson | 2019-03-12 17:13:43 +0100 |
| commit | 43675d20150e65a5a45923a6fcd292e80006dad0 (patch) | |
| tree | a2e5866abb89ebc2a095df4df949c98fc345960c /target | |
| parent | target/hppa: Check for page crossings in use_goto_tb (diff) | |
| download | qemu-43675d20150e65a5a45923a6fcd292e80006dad0.tar.gz qemu-43675d20150e65a5a45923a6fcd292e80006dad0.tar.xz qemu-43675d20150e65a5a45923a6fcd292e80006dad0.zip | |
target/hppa: fix overwriting source reg in addb
When one of the source registers is the same as the destination register,
the source register gets overwritten with the destionation value before
do_add_sv() is called, which leads to unexpection condition matches.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190311191602.25796-2-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/hppa/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6c815e05c2..c4815d7e1a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3031,7 +3031,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, DisasCond cond; in2 = load_gpr(ctx, r); - dest = dest_gpr(ctx, r); + dest = tcg_temp_new(); sv = NULL; cb_msb = NULL; @@ -3047,6 +3047,8 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, } cond = do_cond(c * 2 + f, dest, cb_msb, sv); + save_gpr(ctx, r, dest); + tcg_temp_free(dest); return do_cbranch(ctx, disp, n, &cond); } |