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| author | Peter Maydell | 2019-04-29 18:35:58 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-04-29 18:35:58 +0200 |
| commit | 84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201 (patch) | |
| tree | 0ccca40492c0c20a79d9fe26124fd7223374a045 /target | |
| parent | target/arm: Make sure M-profile FPSCR RES0 bits are not settable (diff) | |
| download | qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.tar.gz qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.tar.xz qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.zip | |
hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-3-peter.maydell@linaro.org
Diffstat (limited to 'target')
0 files changed, 0 insertions, 0 deletions