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| author | Rebecca Cran | 2021-02-16 23:45:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-05 16:17:34 +0100 |
| commit | ed84a60ca80c403749c1fc1bab27c85d8edba39d (patch) | |
| tree | d6fb39031b37706d3ce460f91da5bb1620150223 /target | |
| parent | target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU (diff) | |
| download | qemu-ed84a60ca80c403749c1fc1bab27c85d8edba39d.tar.gz qemu-ed84a60ca80c403749c1fc1bab27c85d8edba39d.tar.xz qemu-ed84a60ca80c403749c1fc1bab27c85d8edba39d.zip | |
target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71f..058672c977 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2217,6 +2217,10 @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_pfr0; t = FIELD_DP32(t, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 = t; + + t = cpu->isar.id_pfr2; + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = t; } #endif } |