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| author | malc | 2010-04-06 00:53:11 +0200 |
|---|---|---|
| committer | malc | 2010-04-06 00:54:22 +0200 |
| commit | a884dcb80451db46b9360c9695b5c55e5d03b16a (patch) | |
| tree | ed2f5944cbd55b20084c0cf0667c268f5b004299 /tcg/ppc | |
| parent | OHCI qdev conversion (diff) | |
| download | qemu-a884dcb80451db46b9360c9695b5c55e5d03b16a.tar.gz qemu-a884dcb80451db46b9360c9695b5c55e5d03b16a.tar.xz qemu-a884dcb80451db46b9360c9695b5c55e5d03b16a.zip | |
tcg/ppc: Implment bswap16/32
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'tcg/ppc')
| -rw-r--r-- | tcg/ppc/tcg-target.c | 75 | ||||
| -rw-r--r-- | tcg/ppc/tcg-target.h | 4 |
2 files changed, 77 insertions, 2 deletions
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index a40883bde0..9fe11bb272 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -328,6 +328,7 @@ static int tcg_target_const_match(tcg_target_long val, #define LWZU OPCD(33) #define STWU OPCD(37) +#define RLWIMI OPCD(20) #define RLWINM OPCD(21) #define RLWNM OPCD(23) @@ -1715,6 +1716,77 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_setcond2 (s, args, const_args); break; + case INDEX_op_bswap16_i32: + /* Stolen from gcc's builtin_bswap16 */ + + /* a1 = abcd */ + + /* r0 = (a1 << 8) & 0xff00 # 00d0 */ + tcg_out32 (s, RLWINM + | RA (0) + | RS (args[1]) + | SH (8) + | MB (16) + | ME (23) + ); + + /* a0 = rotate_left (a1, 24) & 0xff # 000c */ + tcg_out32 (s, RLWINM + | RA (args[0]) + | RS (args[1]) + | SH (24) + | MB (24) + | ME (31) + ); + + /* a0 = a0 | r0 # 00dc */ + tcg_out32 (s, OR | SAB (0, args[0], args[0])); + break; + + case INDEX_op_bswap32_i32: + /* Stolen from gcc's builtin_bswap32 */ + { + int a0 = args[0]; + + /* a1 = args[1] # abcd */ + + if (a0 == args[1]) { + a0 = 0; + } + + /* a0 = rotate_left (a1, 8) # bcda */ + tcg_out32 (s, RLWINM + | RA (a0) + | RS (args[1]) + | SH (8) + | MB (0) + | ME (31) + ); + + /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */ + tcg_out32 (s, RLWIMI + | RA (a0) + | RS (args[1]) + | SH (24) + | MB (0) + | ME (7) + ); + + /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */ + tcg_out32 (s, RLWIMI + | RA (a0) + | RS (args[1]) + | SH (24) + | MB (16) + | ME (23) + ); + + if (!a0) { + tcg_out_mov (s, args[0], a0); + } + } + break; + default: tcg_dump_ops (s, stderr); tcg_abort (); @@ -1776,6 +1848,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_setcond_i32, { "r", "r", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + #if TARGET_LONG_BITS == 32 { INDEX_op_qemu_ld8u, { "r", "L" } }, { INDEX_op_qemu_ld8s, { "r", "L" } }, diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d806fe2fe4..53024282da 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -83,8 +83,8 @@ enum { #define TCG_TARGET_HAS_ext16s_i32 #define TCG_TARGET_HAS_ext8u_i32 #define TCG_TARGET_HAS_ext16u_i32 -/* #define TCG_TARGET_HAS_bswap16_i32 */ -/* #define TCG_TARGET_HAS_bswap32_i32 */ +#define TCG_TARGET_HAS_bswap16_i32 +#define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_andc_i32 |