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* tcg/ppc: Optimize 26-bit jumpsLeandro Lupori2022-10-041-31/+88
* tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]Matheus Kowalczuk Ferst2022-06-202-2/+24
* tcg/ppc: Optimize memory ordering generation with lwsyncNicholas Piggin2022-05-261-3/+6
* tcg/ppc: ST_ST memory ordering is not provided with eieioNicholas Piggin2022-05-261-2/+0Star
* target/ppc: declare vmsumuh[ms] helper with call flagsMatheus Ferst2022-05-261-0/+1
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-5/+5
* tcg/ppc: Implement vector NAND, NOR, EQVRichard Henderson2022-03-042-3/+18
* tcg: Add opcodes for vector nand, nor, eqvRichard Henderson2022-03-041-0/+3
* target/ppc: moved vector even and odd multiplication to decodetreeLucas Mateus Castro (alqotel)2022-03-021-0/+6
* tcg/ppc: Support raising sigbus for user-onlyRichard Henderson2022-02-082-10/+90
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-8/+8
* tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-061-5/+5
* tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-061-4/+4
* tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELFRichard Henderson2021-09-141-3/+18
* tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWINRichard Henderson2021-09-141-4/+4
* tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson2021-07-101-1/+0Star
* tcg/ppc: Use power10 byte-reverse instructionsRichard Henderson2021-06-291-0/+34
* tcg/ppc: Support bswap flagsRichard Henderson2021-06-291-6/+16
* tcg/ppc: Split out tcg_out_bswap64Richard Henderson2021-06-291-30/+34
* tcg/ppc: Split out tcg_out_bswap32Richard Henderson2021-06-291-16/+22
* tcg/ppc: Split out tcg_out_bswap16Richard Henderson2021-06-291-15/+19
* tcg/ppc: Split out tcg_out_sari{32,64}Richard Henderson2021-06-291-4/+13
* tcg/ppc: Split out tcg_out_ext{8,16,32}sRichard Henderson2021-06-291-10/+21
* tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson2021-06-111-0/+2
* tcg: Change parameters for tcg_target_const_matchRichard Henderson2021-06-041-3/+1Star
* tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina2021-03-171-3/+5
* tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson2021-02-021-1/+0Star
* tcg/ppc: Split out constraint sets to tcg-target-con-set.hRichard Henderson2021-02-023-81/+100
* tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson2021-02-021-1/+0Star
* tcg/ppc: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-58/+46Star
* tcg/ppc: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-17/+27
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-131-3/+0Star
* tcg: Increase tcg_out_dupi_vec immediate to int64_tRichard Henderson2021-01-131-13/+24
* tcg: Use tcg_out_dupi_vec from temp_loadRichard Henderson2021-01-131-6/+0Star
* tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson2021-01-071-2/+1Star
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-071-2/+1Star
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-071-1/+0Star
* tcg/ppc: Support split-wx code generationRichard Henderson2021-01-072-24/+31
* tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TBRichard Henderson2021-01-071-3/+2Star
* tcg/ppc: Use tcg_tbrel_diffRichard Henderson2021-01-071-3/+3
* tcg: Add --accel tcg,split-wx propertyRichard Henderson2021-01-071-0/+1
* tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson2021-01-072-9/+9
* tcg: Adjust tcg_register_jit for constRichard Henderson2021-01-071-1/+1
* tcg: Adjust tcg_out_call for constRichard Henderson2021-01-071-4/+4
* tcg: Adjust TCGLabel for constRichard Henderson2021-01-071-2/+2
* tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson2021-01-071-1/+1
* util: Enhance flush_icache_range with separate data pointerRichard Henderson2021-01-071-2/+2
* tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson2021-01-071-0/+1
* util: Extract flush_icache_range to cacheflush.cRichard Henderson2021-01-022-23/+0Star
* tcg: Remove TCG_TARGET_HAS_cmp_vecRichard Henderson2020-10-081-1/+0Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-11-21 14:10:39 +0100