diff options
| author | Richard Henderson | 2020-09-04 00:56:24 +0200 |
|---|---|---|
| committer | Richard Henderson | 2020-10-08 12:57:32 +0200 |
| commit | 74a117906b87ff9220e4baae5a7431d6f4eadd45 (patch) | |
| tree | d99fbe2a152523b0dd5b73fbd22e46aa2bdfd7cf /tcg/riscv | |
| parent | tcg: Move sorted_args into TCGArgConstraint.sort_index (diff) | |
| download | qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.gz qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.xz qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.zip | |
tcg: Remove TCG_CT_REG
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 0a69839adb..d536f3ccc1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'L': /* qemu_ld/qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ #if defined(CONFIG_SOFTMMU) |