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* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-2/+2
* tcg/riscv: Support raising sigbus for user-onlyRichard Henderson2022-02-082-4/+61
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-3/+3
* tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-061-8/+8
* tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-061-2/+2
* tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson2021-09-221-8/+2Star
* tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson2021-07-101-1/+0Star
* tcg/riscv: Remove MO_BSWAP handlingRichard Henderson2021-06-291-31/+33
* tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson2021-06-111-0/+1
* tcg: Change parameters for tcg_target_const_matchRichard Henderson2021-06-041-3/+1Star
* tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina2021-03-171-1/+2
* tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson2021-02-021-1/+0Star
* tcg/riscv: Split out constraint sets to tcg-target-con-set.hRichard Henderson2021-02-023-60/+54Star
* tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson2021-02-021-1/+0Star
* tcg/riscv: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-39/+35Star
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-131-2/+0Star
* tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson2021-01-071-2/+1Star
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-071-2/+1Star
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-071-1/+0Star
* tcg/riscv: Support split-wx code generationRichard Henderson2021-01-072-19/+24
* tcg/riscv: Remove branch-over-branch fallbackRichard Henderson2021-01-071-50/+6Star
* tcg/riscv: Fix branch range checksRichard Henderson2021-01-071-13/+15
* tcg: Add --accel tcg,split-wx propertyRichard Henderson2021-01-071-0/+1
* tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson2021-01-071-1/+1
* tcg: Adjust tcg_register_jit for constRichard Henderson2021-01-071-1/+1
* tcg: Adjust tcg_out_call for constRichard Henderson2021-01-071-3/+3
* tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson2021-01-071-2/+2
* tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson2021-01-071-0/+1
* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-01-061-5/+0Star
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| * util: Extract flush_icache_range to cacheflush.cRichard Henderson2021-01-021-5/+0Star
* | tcg/riscv: Fix illegal shift instructionsZihao Yu2021-01-041-6/+6
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* tcg: Remove TCG_CT_REGRichard Henderson2020-10-081-2/+0Star
* tcg: Drop union from TCGArgConstraintRichard Henderson2020-10-081-7/+7
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-2/+2
* tcg/riscv: Remove superfluous breaksLiao Pingfang2020-07-141-2/+0Star
* tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé2020-01-161-2/+2
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-10/+10
* tcg/riscv: Fix RISC-VH host build failureAlistair Francis2019-07-091-2/+2
* cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson2019-06-101-24/+7Star
* tcg: Create struct CPUTLBRichard Henderson2019-06-101-10/+2Star
* tcg: Return bool success from tcg_out_movRichard Henderson2019-05-131-2/+3
* tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson2019-04-241-4/+12
* tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson2019-04-241-0/+2
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-1/+0Star
* tcg/riscv: enable dynamic TLB sizingRichard Henderson2019-01-282-71/+55Star
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-0/+1
* tcg/riscv: Add the target init codeAlistair Francis2018-12-251-0/+31
* tcg/riscv: Add the prologue generation and register the JITAlistair Francis2018-12-251-0/+111
* tcg/riscv: Add the out op decoderAlistair Francis2018-12-251-0/+496
* tcg/riscv: Add direct load and store instructionsAlistair Francis2018-12-251-0/+158
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