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| author | Richard Henderson | 2020-10-16 23:07:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-20 17:12:00 +0200 |
| commit | ea04dce7bb4ccd3e464e5189c0d6d53510b7c212 (patch) | |
| tree | 0e323ac3696644738504bf4fcc895ab0c496f160 /tests | |
| parent | accel/tcg: Add tlb_flush_page_bits_by_mmuidx* (diff) | |
| download | qemu-ea04dce7bb4ccd3e464e5189c0d6d53510b7c212.tar.gz qemu-ea04dce7bb4ccd3e464e5189c0d6d53510b7c212.tar.xz qemu-ea04dce7bb4ccd3e464e5189c0d6d53510b7c212.zip | |
target/arm: Use tlb_flush_page_bits_by_mmuidx*
When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.
The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.
Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions